Principal PLL Analog IC Design Engineer

Applied: No

Date Posted: Thursday, June 29th, 2017
Job Location: San Jose, CA
Pay Rate: Competitive
Employment Type: Full-time
Job Duration: Permanent
Required Skills: See job description

Job Description:

Job Description

RESPONSIBILITIES:
A Semiconductor company in the San Jose, CA area is looking for a Principal Analog Mixed Signal Design Engineers with strong Fractional-N-Sythesizer experience. Position is a senior member of the high performance PLL Synthesizer design team. We are working directly with the Hiring Manager. Our client will provide a relocation package if needed. This Analog IC Design Engineering position will provide key contributions to state of the art PLL's for use in high performance networking and communications and/or Audio products. Responsibilities of the position include product definition, design, layout, lab verification, and releases to production.

REQUIREMENTS:
* Candidates must have a MSEE or Ph.D. with at least 10-15+ years of Analog IC Design work experience at an extensive high performance-level
* Expert level PLL Design experience is required
* An excellent track record in CMOS and/or BiCMOS IC Design is required
* Experience in designing low phase noise integer PLLs, fractional-N synthesizers is required
* Experience designing Fractional-N and Integer-N PLLs for high performance Synthesizers is required
* Candidates must be experienced designing high performance LC and Ring Oscillator VCOs
* Project Lead experience is a plus
* RF / Wireless experience is also a plus

Other related experience in the design of various PLLs, crystal oscillators, VCXOs, on-chip regulators, DACs and ADCs are pluses. The qualified applicant will have strong communications, strong work ethic, and the ability to work individually and within a team environment.

Posted by:

Kforce Inc
1001 E. Palm Ave.
Tampa, FL 33605
https://www.kforce.com

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